System and method for pulse current plating

ABSTRACT

According to one embodiment of the present invention, a method for electroplating electronic devices is disclosed which includes placing the outer surface of a substrate in contact with a solution comprising a conductive material. An electrical current is passed through the solution and the substrate so as to cause the conductive material to deposit on the substrate under the electromotive force caused by the electrical current. The level of the electrical current is varied from a first current level to a second current level to provide for differing rates of deposition of the conductive material on the substrate. The second current level provides a relaxation period to allow the conductive material deposited on the substrate to come to equilibrium.

RELATED APPLICATIONS

[0001] This application is related to and claims the benefit of co-pending U.S. Provisional Application Serial No. 60/441,556 entitled Method for Electro-Deposition of Lead Free Alloys by Pulse Current Plating, (TI Docket No. TI-35798PS), filed on Jan. 21, 2003.

TECHNICAL FIELD OF THE INVENTION

[0002] This invention relates in general to the field of electronic device processing and more particularly to an improved system and method for current pulse plating in integrated devices.

BACKGROUND OF THE INVENTION

[0003] As integrated circuit features become smaller, the capacity of these features to carry the current necessary for the operation of the integrated circuit device is reduced. As such, device designers have turned to more exotic materials within these integrated structures. For example, bumps and interconnects are now constructed from electro-positive metal alloys, such as Silver and Copper, which are more difficult materials to work with than prior conductive materials. The metal alloys are difficult to deposit on a surface of a device without supplying electroplating current. Because the metal composites comprising the metal alloys typically plate at different voltages, the surfaces of the integrated structures may be highly irregular and nonuniform in thickness. Additionally, the bumps and interconnects may exhibit significant internal tensile stress. This increased tensile stress may cause the metal alloy to delaminate from the surfaces of the integrated circuit. Additionally, even under carefully controlled conditions increased temperatures may create unwanted carrier migration and other defects within the integrated circuit.

SUMMARY OF THE INVENTION

[0004] In accordance with the teachings of the present invention a system and method of electroplating electronic devices is described that substantially eliminates or reduces problems associated with prior techniques and systems.

[0005] According to one embodiment of the present invention, a method for electroplating electronic devices is disclosed which includes placing the outer surface of a substrate in contact with a solution comprising a conductive material. An electrical current is passed through the solution and the substrate so as to cause the conductive material to deposit on the substrate under the electromotive force caused by the electrical current. The level of the electrical current is varied from a first current level to a second current level to provide for differing rates of deposition of the conductive material on the substrate. The second current level provides a relaxation period to allow the conductive material deposited on the substrate to come to equilibrium.

[0006] An important technical advantage of the present invention inheres in the fact that the relaxation period during the deposition process allows the conductive material to come to a state of equilibrium. As a result, the atoms of conductive material deposited on the electronic device may form crystallized blocks. A further technical advantage of certain embodiments or the present invention may include an increase in the uniformity of the surface of the conductive material. Another technical advantage of certain embodiments of the present invention may include that the tensile stress within the conductive material is substantially reduced. Accordingly, the occurrence of delamination and other defects within the conductive material may be reduced.

BRIEF DESCRIPTION OF THE DRAWINGS

[0007] A more complete understanding of the present invention may be acquired by referring to the accompanying figures in which like reference numbers indicate like features and wherein:

[0008]FIG. 1 is a schematic diagram of an electroplating system constructed according to the teachings of the present invention;

[0009] FIGS. 2A-2D are cross-sectional diagrams illustrating the various layers formed on the outer surface of an electrical device according to the teachings of the present invention; and

[0010]FIG. 3 is a graphical illustration of an example pulse plating technique according to the teachings of the present invention;

[0011] FIGS. 4A-4C are graphical illustrations of various example pulse plating techniques used to vary the current during an electroplating process according to the teachings of the present invention; and

[0012] FIGS. 5A-5D are graphical illustrations of further example pulse plating techniques that may be used during the electroplating process according to the teachings of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

[0013] Copper and various other conductive metals and metal alloys are typically deposited on a semiconductor substrate by a process of electroplating. In this process the workpiece is typically submerged in a liquid solution which includes the conductive material to be deposited on the surface. FIG. 1 is a schematic illustration of an electroplating system 10, which is operable to electroplate a conductive film onto a surface of a workpiece 12. System 10 includes a solution container 14 that contains a liquid solution 16 into which the workpiece 12 can be placed during the electroplating process. The workpiece 12 is physically held in place by an electrically conductive chuck 18. Chuck 18 is connected physically to a rotator 20 that is controlled by a rotation control unit 22. Chuck 18 is electrically connected to a current source 24 through a current controller 26. Current source 24 is connected electrically to the solution 16 to complete the circuit. As will be discussed herein, current source 24 may be operable to induce current both to and from the solution 15 to the workpiece 12 so as to cause the conductive material to deposit on the surface of workpiece 12. As such, although a particular polarity is illustrated in FIG. 1, it should be understood that such polarity may be reversed if necessary during the plating operation.

[0014] In general, the workpiece 12 is lowered into the liquid solution 16 and may be rotated by rotator 20 under the control of rotation control 22. Under some circumstances, the workpiece 12 may not be rotated during the initial or other phases of the plating operations. If or when the workpiece 12 is rotated, the speed of the rotation can effect the rate at which the metallic solution is deposited onto the workpiece 12 as well as the character of the film deposited. When the workpiece 12 is submerged in the solution 16 a current is able to flow as controlled by the current controller 26. The electroplating process of depositing the film on the workpiece 12 can be controlled by the amount of current that is allowed to flow by controller 26. In general, the amount of current necessary to deposit the film on workpiece 12 may depend on the composition of the conductive film being deposited. For example, because different metal alloys have different plating voltages, the amplitude and frequency of current necessary to deposit the conductive film may depend on the plating voltage of the conductive materials.

[0015] While electroplating techniques have been known in the past, they have not been well adapted to uniformly deposit conductive films, such as metal alloys. To achieve a uniform surface and effectively homogenous mixture of the metals comprising the metal alloy, the amount of current may be varied to control the rate at which the metals are electroplated on the surface of workpiece 12. One potential application of the electroplating techniques and systems of the present invention includes varying the amount of current used during the electroplating of conductive materials to form conductive studs and bumps on the outer surface of workpiece 12. FIGS. 2A-2D are cross-sectional diagrams illustrating the various layers formed on the outer surface of an electronic device. Specifically, FIG. 2A illustrates electrical device 30 after the initial formation of a stud 32 and a bump 34 on the surface of electrical device 30. Stud 32 and bump 34 may cooperatively operate to form an interconnect between electrical device 30 and other components of an integrated circuit. For example, stud 32 and bump 34 may form an interconnect between electrical device 30 and a contact, pad, or bump associated with another component of the integrated circuit.

[0016] Stud 32 and bump 34 are supported on several intermediary layers formed on a base layer 36. Base layer 36 may comprise an inter-metal dielectric that operates to support later formed conductive layers. According to particular embodiments, base layer 36 may comprise fluorinated silicate glass, organosilicate glass, or other suitable dielectric polymer. A first interlevel insulator layer 38 may be formed on the outer surface of base layer 36 using conventional semiconductor fabrication processes. For example, first interlevel insulator layer 38 may be formed on the outer surface of base layer 36 using deposition techniques. First interlevel insulator layer 38 forms a protective over-coat on the surface of base layer 36. In particular embodiments, first interlevel insulator layer 38 is of a thickness on the order of 0.5 to 2.0 microns. Such dimensions, however, are merely exemplary; it is contemplated that first interlevel insulator layer 38 may be of any appropriate thickness for supporting any subsequently formed layers. Typically, first interlevel insulator layer 38 include a dielectric material. In particular embodiments, first interlevel insulator layer 38 may include fluorinated silicon oxide, silicon nitride, silicon-oxy-nitride, or any other appropriate dielectric material. A via may be formed in first interlevel insulator layer 38 through conventional photolithographic and etching processes. The via may form a trench through a portion of first interlevel insulator layer 38 to expose a portion of the outer surface of base layer 36.

[0017] The via or trench formed in first interlevel insulator layer 38 may then be filled with one or more layers of conductive material to form inner conductive layer 40. Inner conductive layer 40 comprises a metal pad and may be formed using any conventional semiconductor fabrication processes such as deposition or electroplating. Inner conductive layer 40 may be comprised of copper, aluminum, nickel, or another suitable conductive metal or combinations thereof. In particular embodiments, the deepest portion of inner conductive layer 40 may be of a thickness on the order of approximately 2,000 to 8,000 Angstroms. It is contemplated, however, that inner conductive layer 40 may be of any appropriate thickness for innerconnecting various components of electrical device 30. Because a portion of inner conductive layer 40 may touch or otherwise connect with base layer 36, inner conductive layer 40 may enable current to pass from one semiconductor component to another.

[0018] A second interlevel insulator layer 42 may be formed on the outer surfaces of first interlevel insulator layer 42 and inner conductive layer 40 using conventional semiconductor fabrication processes. For example, second interlevel insulator layer 42 may be formed on the outer surfaces of first interlevel insulator layer 38 and inner conductive layer 40 using deposition techniques. Second interlevel insulator layer 42 may comprise an organic stress-relieving dielectric. In particular embodiments, second interlevel insulator layer 42 may comprise poly-Benzo-Cyclo-Butene (BCB), poly-Benzo-Oxylane (PBO), Polyimide (PIQ), or other polyamide, polyamicacid, polyenzoxazoles, polybenzocyclobutene, or polysiloxane. Although second interlevel insulator layer 42 may be comprised of the same material as first interlevel insulator layer 38, first and second interlevel insulator layers 38 and 42 need not be comprised of the same dielectric material. For example, first interlevel insulator layer 38 may comprise fluorinated silicate glass and second interlevel insulator layer 42 may comprise organosilicate glass. Alternatively, first and second interlevel insulator layers 38 and 42 may both comprise fluorinated silicate glass. In particular embodiments, second interlevel insulator layer 42 is of a thickness on the order of 1 to 10 microns. Such dimensions, however, are merely exemplary; it is contemplated that second interlevel insulator layer 42 may be of any appropriate thickness suitable for supporting subsequently formed layers. A via may be formed in second interlevel insulator layer 42, preferably through suitable photolithographic and etching processes. The via may form a trench through a portion of second interlevel insulator layer 42 to expose a portion of the outer surface of inner conductive layer 40.

[0019] A seed layer 44 may be formed on the outer surfaces of second interlevel insulator layer 42 and inner conductive layer 40. The primary purpose of seed layer 44 is to adhere to the inner conductive layer 40 and to provide a nucleation layer for electroplated film. Seed layer 44 may also act as a contact for electroplate material. As such seed layer 44 may be much thinner than second interlevel insulator layer 42. If, for example, second interlevel insulator layer 42 has a thickness on the order of 1 to 10 microns, seed layer 44 may have a thickness of the order of 2,000 to 10,000 Angstroms. Seed layer 44 may comprise an under-bump metallurgy (UBM) and may include a stack of metals and/or metal alloys. Example metals that may be used include titanium, tungsten, copper, nickel, vanadium, cobalt, chromium, gold, or suitable combinations of the above. Thus, many modifications and substitutions may be made to the formation of the interconnect. All such modifications and substitutions are within the scope and spirit of the present invention.

[0020] A photoresist layer 46 may be formed on the outer surface of seed layer 44. Photoresist layer 46 may be coated and patterned over seed layer 44, resulting in a dual damascene via pattern over seed layer 44. Photoresist layer 46 is a photo-imagible polymer material that may be used to pattern small dimensions on the surface of electrical device 30. Examples of companies providing the materials comprising photoresist layer 46 include Shipley, Clariant, and Shinetsu. Thus, while photoresist layer 46 may be initially deposited on the surface of electrical device 30 to substantially cover seed layer 44, portions of photoresist layer 46 may be selectively etched or patterned using photo-lithography such that a portion of seed layer 44 overlying inner conductive layer 40 may be exposed. In particular embodiments, photoresist layer 44 may be of a thickness on the order of approximately 10 to 100 microns. However, photoresist layer 46 may be any appropriate thickness suitable for performing via patterning.

[0021] Stud 32 may be formed to fill a portion of the dual damascene via formed over seed layer 44. Thus, stud 32 may be supported on either side by photoresist layer 46 and from beneath by seed layer 44. Stud 32 may include electroplate material deposited on the seed layer 44 by suitable electroplating processes. In particular embodiments of the present invention, the electroplating process used to form stud 32 may include varying the level of electrical current of current source 24 using controller 26. The level of current may be varied as the material comprising stud 32 is deposited on the surface of seed layer 44. As described above with regard to FIG. 1, the varied levels of current may effect the rate and character of deposition of stud 32.

[0022] In particular embodiments, the electroplating process may include beginning the deposition of stud 32 at a first current level. At the first current level, the material of stud 32 may be deposited on seed layer 44. Thus, the first current level may include a cathodic current. The electroplate rate may then be varied to a second current level. The second current level may result in the deposition of stud 32 at a rate slower or faster than the first current level. According to particular embodiments, the second current level may be sufficiently low so as to stop or substantially slow the deposition of the electroplate material. In this case, the second current level may provide a relaxation period that allows the electroplate material to come to a state of equilibrium. At a state of equilibrium, the atoms of electroplate material deposited on seed layer 44 may form crystallized blocks, which may increase the uniformity of the surface of the electroplate material and decrease intrinsic tensile stress in the electroplate material. Thus, stud 32 may be deposited on the device 30 in a manner that results in a more uniform surface and improves the homogenous composition of stud 32.

[0023] In particular embodiments, the relaxation period may last from 0.1 to 50 seconds. Following the crystallization of the electroplate material comprising stud 32, controller 26 may increase the current level from current source 24 to a third current level. The third current level may be a cathodic (−) or anodic (+) current that is more than, less than, or equal to the first current level. Thus, electroplate material comprising stud 32 may be deposited or removed at the third current level at a rate that is more or less than the rate at which it was deposited at the first current level. Controller 26 may vary the current level from current source 24 as appropriate for the remaining deposition of electroplate material to form stud 32. Alternatively, the current from current source 24 may be pulsed for the remaining deposition of stud 32. The electroplate material comprising stud 32 may include copper, nickel, or other appropriate lead-free metal or metal alloys of relatively high electrical conductivity. In various embodiments, stud 32 is of a thickness on the order of 1 to 15 microns. In particular embodiments, stud 32 may be of a thickness on the order of 6 to 10 microns. Such dimensions, however, are merely exemplary. Stud 32 may be of any appropriate thickness suitable for supporting subsequently formed bump 34. Due to the high electrical conductivity of stud 32, stud 32 may form an interconnection between one semiconductor component and another to allow current to pass between the semiconductor components. For example, stud 32 may form an interconnection between inner conductive layer 40 and subsequently formed bump 34 and devices electrically coupled thereto.

[0024] Bump 34 may be formed to fill any remaining portion of the dual damascene via formed over seed layer 44. Additionally, bump 34 may form a protruding dome partially covering portions of the outer surface of photoresist layer 46. As described above, bump 34 may be supported by stud 32. Bump 34 may also be at least partially supported by photoresist layer 46. Similar to stud 32, bump 34 may include electroplate material deposited by suitable electroplating processes. Also similar to the formation of stud 32, particular embodiments may include the formation of bump 34 using varying levels of electrical current to effect the rate of deposition of the electroplate material comprising bump 34. In particular embodiments, the electroplating process may include beginning the deposition of bump 34 at a first current level. At the first current level, the material of bump 34 may be deposited on stud 32. The electroplate rate may then be varied to a second current level. The second current level may result in the deposition of stud 32 at an electroplate rate that is slower or faster than the first current level. According to particular embodiments, the second current level may be sufficiently low so as to stop or substantially slow the deposition of the electroplate material forming bump 34. The second current level may provide a relaxation period that allows the electroplate material comprising bump 34 to come to a state of equilibrium to allow crystallized blocks to form in the electroplate material. The relaxation period may increase the composition uniformity of the electroplate material forming bump 34 and decrease tensile stress in bump 34. Thus, bump 34 may be deposited on electrical device 30 in a manner that decreases occurrences of delamination within the layers forming bump 34.

[0025] In particular embodiments, the relaxation period may last from 0.001 to 5.0 seconds. Following the crystallization of the electroplate material, during the relaxation period the controller 26 may resume the electroplate process at a third current level. The third current level may be anodic or cathodic current. The third current level may be more than, less than, or equal to the first current level. Where the third current level is a cathodic current, electroplate material may be deposited to continue the formation of bump 34 at a rate that is more or less than the rate at which the material forming bump 34 was deposited at the first current level. The current level may be varied as appropriate for the remaining deposition of electroplate material to form bump 34. Alternatively, where the third current level comprises an anodic current, portions of electroplate material may be removed from bump 34.

[0026] In particular embodiments, bump 34 is of a thickness on the order of 50 to 150 microns. Such dimensions, however, are merely exemplary. Bump 34 may be of any appropriate thickness suitable for supporting providing an interconnect between electrical device 30 and another integrated circuit device. The electroplate material used to form bump 34 may include tin, lead, antimony, silver, bismuth, indium, zinc, copper, or their alloys. Alternatively, electroplate material used to form bump 34 may include any combination of these or other appropriate conductive metals. Regardless of the particular conductive material used to form bump 34, the composition of the electroplate material may be characterized as including a low melting temperature and/or other specific qualities to aid in the further formation of bump 34.

[0027]FIG. 2B illustrates electrical device 30 after photoresist layer 46 is removed from the outer surface of electrical device 30. Photoresist layer 46 may be removed using a solvent that is selective to photoresist layer 46. Thus, in particular embodiments, photoresist layer 46 may be stripped away using conventional anisotropic or isotropic etching processes. As illustrated, the removal of photoresist layer 46 exposes lateral walls 50 of bump 34 and a portion of lateral walls 52 of stud 32. Removal of photoresist layer 46 may also expose an unsupported portion 54 on each side of bump 34.

[0028]FIG. 2C illustrates electrical device 30 after electrical device 30 is heated to cause bump 34 to melt or otherwise become marginally fluid. The fluid nature of bump 34 during heating causes portions of bump 34 to migrate to substantially surround the outer surface of stud 32. In particular embodiments, electrical device 30 may be heated in conventional semiconductor fabrication ovens. For example, electrical device 30 may be heated in an Industry Reflow oven. Temperatures may vary on the order of 180 to 280° C. As illustrated, the heating or otherwise melting of bump 34 may result in unsupported portions 54 and other portions of bump 34 to migrate to substantially surround formerly exposed lateral walls 52 of stud 32. Accordingly, lateral walls 52 of stud 32 may support portions of bump 34 to add increased stability to bump 34.

[0029] The following table represents the melting points for example conductive materials that may be used to form stud 32 and/or bump 34. Known Composition Melting Temp. (° C.) 95% Sn/5% Ag 221-240 99.3% Sn/0.7% Cu 227 91.8% Sn/4.8% Bi/3.4% Ag 221 94% Sn/4% Bi/2% Ag 203.6-231.1 95.5% Sn/3.9% Ag/0.6% Cu 218

[0030] The above compositions, however, are just a sample of the candidates that may be used to form stud 32 and/or bump 34.

[0031]FIG. 2D illustrates electrical device 30 after melting and after seed layer 44 is removed from the exposed outer surfaces 56 of second interlevel insulator layer 42 on either side of bump 34. The exposed portions of seed layer 44 may be removed using a solvent that is selective to seed layer 44. Thus, in particular embodiments, exposed portions of seed layer 44 may be stripped or etched away using conventional anisotropic or isotropic etching processes. As illustrated, the removal of the exposed portions of seed layer 44 exposes outer surfaces 56 of second interlevel insulator layer 42 on either side of bump 34. In this configuration, bump 34 may form an interconnection allowing current to flow between electrical device 30 and another semiconductor component.

[0032]FIG. 3 is a graphical illustration of an example pulse plating technique that may be used to form stud 32 and bump 34. As described above, stud 32 and bump 34 may be formed using plating processes that include applying the conductive materials forming stud 32 and bump 34 using pulse plating. Pulse plating includes interrupting the application of current from current source 24 with relaxation periods such that the application of current is periodic during the plating process. As such, pulses of current 100 may be applied to electrical device 30 from current source 24. The pulses of current 100 may be separated by relaxation periods 102. Current 100 may be applied at a peak amount for a first interval of time followed by a relaxation period 102 for a second interval of time. Relaxation period 102 may allow the conductive material being applied to electrical device 30 to relax or otherwise enter a state of equilibrium. In particular embodiments, relaxation periods 102 may allow crystallized blocks to form in the conductive material being applied to electrical device 30.

[0033] The interval of time and peak current level associated with the application of current 100 may vary depending on the plating voltage of the conductive material being applied to electrical device 30. Because the conductive material does not plate immediately as current 100 is applied, the interval of time during which current 100 is applied may be that which is necessary to plate the particular conductive material and apply a desired portion of the conductive material to the surface of electrical device 30 to begin or continue formation of stud 32 or bump 34.

[0034] Depending on the particular conductive material being applied to electrical device 30, current 100 may be applied for an interval on the order of 0.001 to 5.0 seconds. In the illustrated example, each pulse of current 100 is applied for a duration of 5 milli-seconds at a peak current level of 75 Amps.

[0035] The interval of time and peak current level associated with relaxation period 102 may also depend on the particular conductive material being applied to electrical device 30. As described above, relaxation period 102 may allow the electroplate material comprising stud 32 and/or bump 34 to come to a state of equilibrium to allow crystallized blocks to form in the electroplate material. Accordingly, the duration of relaxation period 102 may be the amount of time appropriate to allow crystallized blocks to form in the particular conductive electroplate material. For example, depending on the particular conductive material being applied to electrical device 30, relaxation period 102 may include reducing of ceasing the application of current 100 for an interval on the order of 0.001 to 5.0 seconds. In the illustrated example, each relaxation period 102 comprises an interval of 45 milli-seconds. The reduced current for relaxation periods 102 may increase the uniformity of the surface of the electroplate material and decrease tensile stress in stud 32 and/or bump 34.

[0036] An average current measurement may be calculated for a pulse plating process using the amount of peak current applied, the interval of time associated with each application of current 100, and the interval of time associated with each relaxation period 102. The average current measurement is merely the calculation of the average current used to apply the conductive material during the duration of plating process. In the illustrated example, the peak current of 75 Amps is applied constantly for an interval of 5 milli-seconds. Each application of current 100 is followed by a relaxation period 102 of 45 milli-seconds. Accordingly, current 100 is applied {fraction (1/10)} of the time during the plating process. As such, the average current may be calculated as {fraction (1/10)} of the peak current. In the illustrated example, the average current applied during the plating process is 7.5 Amps. The values illustrated in FIG. 3, however, are merely exemplary. As described above, the peak current value and the intervals of time used for application of current 100 and relaxation period 102 may vary as appropriate to the pulse plating process.

[0037] FIGS. 4A-4C are graphical illustrations of various example pulse plating techniques used to vary the current during an electroplating process according to the teachings of the present invention. The various examples illustrate that the current applied may be cathodic (−) or anodic (+). As described above, cathodic current generally is used to apply conductive material, while anodic current is generally used to remove conductive material. Conductive material may be removed where appropriate to increase the uniformity in the surface of the conductive material. The various examples also illustrate that the current may be pulsed in a constant manner or may be varied and that the time intervals associated with the application of the current and the relaxation periods may be varied.

[0038] Specifically, FIG. 4A illustrates alternating cathodic current 120 and anodic current 122 with brief relaxation periods 124. During a typical cycle of the plating process, cathodic current 120 may be applied for a first interval of time 126. As cathodic current 120 is applied, the particular conductive material forming stud 32 or bump 34 is electroplated to electrical device 30. The application of cathodic current 120 is followed by a relaxation period 124 for a second interval of time 128. Although second interval of time 128 is shown as being substantially less than first interval of time 126, second interval of time 126 may be of any length of time appropriate for allowing the conductive material applied during first interval of time 126 to enter a state of equilibrium. Accordingly, second interval of time 128 may be more than, less than, or equal to first interval of time 126.

[0039] Following relaxation period 124 anodic current 122 is applied for a third interval of time 130. As anodic current 122 is applied, a portion of the conductive material applied during first interval 126 may be removed from the surface of electrical device 30. The removal of a portion of conductive material may result in a more uniform and stable structure of the conductive material comprising stud 32 and/or bump 34. The length of third interval of time 130 depends upon the amount of deplating required. Additionally, it should be understood that the use of anodic current 122 to result in deplating is purely optional and may be omitted if the initial plated layer will not withstand such an operation or if it is not desirable due to other considerations. In particular embodiments, the plating cycle may conclude with a second relaxation period 132 for a fourth interval of time 134. Although fourth interval of time 134 is illustrated as being substantially equal to second interval of time 128 associated with first relaxation period 124, fourth interval of time 134 may be any length of time appropriate for allowing the conductive material remaining on electrical device 130 after anodic current 122 to enter a state of equilibrium. Accordingly, fourth interval of time 128 may be more than, less than, or equal to second interval of time 126. Alternatively, second relaxation period 134 may be omitted altogether. The cycle may continue as illustrated by repeating alternating applications of cathodic current 120 and anodic current 122 separated by relaxation periods 128 until stud 32 and/or bump 34 is formed.

[0040]FIGS. 4B and 4C are included to further illustrate variations that may be made to the pulse plating process. In FIG. 4B, the cathodic currents 120 and anodic currents 122 are pulsed. Each cathodic current 120 and anodic current 122 is followed by a relaxation period 124. Additionally, the intervals of time associated with the application of the cathodic currents 120, anodic currents 122, and relaxation periods 124 have been varied. Specifically, the intervals of time associated with anodic current 122 are less than the intervals of time associated with cathodic currents 120.

[0041] In FIG. 4C, the intervals of time associated with cathodic currents 120 are varied cycle to cycle. During the first cycle of pulsed cathodic currents 120, the interval of time for each pulse of cathodic current 120 is substantially constant. In contrast, the interval of time for each pulse of cathodic current 120 is varied during the second cycle of pulsed cathodic currents 120. FIG. 4C is included to illustrate that the amplitude of negative current applied during pulses of cathodic current 120 may be varied from the amount of negative current applied during pulses of anodic current 122. Thus, more or less Amplitudes of current may be desired during the deplating portion of the cycle than is during the plating portion of the cycle.

[0042] FIGS. 5A-5D are graphical illustrations of further examples of pulse plating techniques that may be used during the electroplating process according to the teachings of the present invention. Specifically, FIGS. 5A-5D are included to illustrate how varying the intervals of time 200 of relaxation periods 202 effects the average current applied during a plating cycle. In FIG. 5A, each interval of time 204 associated with the application of current 206 is approximately equal to each interval of time 200 associated with relaxation periods 202. Accordingly, current 206 may be said to be applied during 50% of the plating cycle. Because each pulse of applied current 206 is of the same approximate amplitude, the average current applied over the entire plating cycle may be calculated as 50% of current 206. As such, the average current applied over the plating cycle is half of current 206.

[0043] In contrast, FIG. 5B illustrates a plating cycle that includes more time spent in a relaxation period than in plating or deplating. In the illustrated embodiment, each interval of time 210 associated with relaxation periods 212 is approximately twice each interval of time 214 associated with the application of current 216. Accordingly, current 216 may be said to be applied during 25% of the plating cycle. Because each pulse of applied current 216 is of the same approximate amplitude, the average current applied over the entire plating cycle may be calculated as 25% of current 216. FIG. 5C illustrates a similar 25% plating cycle where the peak current has been substantially increased. The interval of time 220 associated with relaxation periods 222 remains approximately twice each interval of time 225 associated with the application of current 226. Because substantially more amplitudes of current 226 are applied during each pulse, however, the average current applied over the entire plating cycle also substantially increases.

[0044]FIG. 5C illustrates a varied frequency plating cycle. The illustrated plating cycle may be broken into a first section 300 and a second section 302. Within first section 300, the interval of time 300 associated with each relaxation period 312 is substantially equal to the interval of time 314 associated with each application of current 316. Accordingly, similar to FIG. 5A, first section 300 represents a 50% plating cycle. Because each pulse of applied current 316 is of the same approximate amplitude, the average current applied over first section 300 of the plating cycle may be calculated as 50% of current 316. With regard to second section 302, the alternating pulses of current 326 and relaxation periods 322 occur with greater frequency. The intervals of time 320 associated with each relaxation period 322, however, remains substantially equal to the intervals of time 324 associated with each application of current 326. As such, second section 302 also represents a 50% plating cycle. Because each pulse of applied current 316 and 326 is of the same approximate amplitude, the average current applied over the is unchanged by the varying frequency. Accordingly, in the illustrated embodiment, the varied frequency affects only the duration of the pulses of current 316 and 326 and the duration of the relaxation periods 312 and 322. The average current over the entire cycle is unchanged.

[0045] Accordingly, a variety of plating techniques have been described which may be used alone or in combination to contribute to the creation of a conductive layer which may form stud 32 or bump 34. Because the techniques described allow the conductive material to come to a state of equilibrium, crystallized blocks may be allowed to periodically form in the many layers of conductive material forming stud 32 or bump 34. Accordingly, the metals forming the conductive material may be more evenly and uniformly distributed to form a more homogenous mixture. Additionally, the tensile stress within the conductive material may be reduced such that delamination is prevented within the layers of conductive material forming stud 32 or bump 34. Where appropriate anodic current may be periodically applied. Anodic current may result in deplating of the conductive material to further increase the uniformity of the layers of conductive material.

[0046] Although the present invention has been described in detail it should be understood that various changes, alterations, substitutions and modifications can be made to the teachings disclosed herein without departing from the spirit and scope of the present invention which is solely defined by the appended claims. 

What is claimed is:
 1. A method for electroplating electronic devices, comprising: placing an outer surface of a substrate in contact with a solution comprising a conductive material, passing electrical current through the solution and the substrate so as to cause the conductive material to deposit on the substrate under the electromotive force caused by the electrical current; varying the level of the electrical current from a first current level to a second current level to provide for differing rates of deposition of the conductive material on the substrate; wherein the second current level provides a relaxation period to allow the conductive material deposited on the substrate to come to an equilibrium.
 2. The method of claim 1, wherein the second current level is no current applied for time interval comprising 0.001 to 5.0 seconds.
 3. The method of claim 1, wherein the first current is a cathodic current.
 4. The method of claim 1, wherein the first current is a cathodic current applied for a time interval comprising 0.001 to 5.0 seconds.
 5. The method of claim 1, and further comprising varying the level of the electrical current from the second current level to a third current level.
 6. The method of claim 5, wherein the second current level is no current, the third current level comprising a cathodic current applied.
 7. The method of claim 5, wherein the second current level is no current, the third current level comprising a cathodic current applied for a time interval comprising 0.001 to 5.0 seconds.
 8. The method of claim 5, wherein the second current level is no current, the third current level comprising an anodic current level.
 9. The method of claim 1, wherein the conductive material comprises a bump on the outer surface of the substrate.
 10. The method of claim 1, wherein the conductive material comprises a stud on the outer surface of the substrate.
 11. A system for electroplating electronic devices comprising: a container operable to hold a solution comprising a conductive material; a chuck operable to hold the workpiece in contact with the solution; a rotator coupled to the chuck and operable to rotate the chuck and the workpiece in the solution; a rotation controller coupled to the rotator and operable to control the rate of rotation of the workpiece in the solution; a current source coupled to the solution and to the workpiece and operable to supply an electric current traveling through the solution and the workpiece; a current flow controller coupled to the power supply and operable to control the amount of electric current flowing through the solution and the workpiece at any given time, the controller operable to change the amount of current flowing through the solution and the workpiece from a first current level to a second current level to provide for differing rates of deposition of the conductive material on the substrate, the second current level providing a relaxation period to allow the conductive material deposited on the substrate to come to an equilibrium.
 12. The system of claim 11, wherein the second current level is no current applied for time interval comprising 0.001 to 5.0 seconds.
 13. The system of claim 11, wherein the first current is a cathodic current.
 14. The system of claim 11, wherein the first current is a cathodic current applied for a time interval comprising 0.001 to 5.0 seconds.
 15. The system of claim 11, wherein the current flow controller is further operable to vary the level of the electrical current from the second current level to a third current level.
 16. The system of claim 15, wherein the second current level is no current, the third current level comprising a cathodic current.
 17. The system of claim 15, wherein the second current level is no current, the third current level comprising a cathodic current applied for a time interval comprising 0.1 to 50 seconds.
 18. The system of claim 11, wherein the second current level is no current, the third current level comprising an anodic current level.
 19. The system of claim 11, wherein the conductive material comprises a bump on the outer surface of the substrate.
 20. The system of claim 11, wherein the conductive material comprises a stud on the outer surface of the substrate. 